| Section 4: Decoding the Pulse Stream | |||||
 |  | | 4 | | Decoding the Pulse Stream Inside the Receiver |
| | | 4.1 | | The Flip-Flop Circuit |
| | | 4.2 | | Separating the Channels |
| | | 4.3 | | A Practical Example |
| | | 4.4 | | Defining the Command Signal |
How R/C Works -
Thinking Inside the R/C Box
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How R/C Works - Thinking Inside the R/C Box |
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| 4 Decoding the Pulse Stream Inside the Receiver: Without getting into the RF components of the receiver, let's assume that the RF carrier has been received, demodulated, and reproduced inside the receiver. The receiver must generate separate pulses that represent the same pulse widths that the transmitter had originally generated for each channel. Timing information for all of the separate channels is contained within the single baseband signal - now it's time to split it up into its separate channel components. This job is performed by the bistable multivibrator, or flip-flop circuit. | ||
| 4.1 The Flip-Flop Circuit: There is a digital logic circuit called a flip-flop, otherwise known as a bistable multivibrator. The flip-flop, in this example, has a single output and 2 inputs. The 2 inputs, called D and CLOCK, work together to define how the output, called Q, behaves. The D input is used to define the state of the output on the next low to high transition of the CLOCK input. For this example, the CLOCK input only recognizes low to high transitions and none other. If the D input is high, and the clock transitions from low to high, then the output will be high immediately after the CLOCK transition occurs. If Q was already high prior to the CLOCK transition then the output will not change. Likewise, if D is low prior to the CLOCK transition then the output will be low after the transition occurs. Under no circumstances will the output change state as a result of a high to low CLOCK transition regardless of the state of the D input. The flip-flop is a common building block in digital circuits. The circuit described here is called a "D" flip-flop because the Q output assumes the state of the D input upon each valid CLOCK edge. |
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| In Figure 12 several states are shown that describe the operation of the flip-flop: State 1: Assume initial conditions: Q and CLOCK inputs are low, D, PRESET and CLEAR inputs are high. Under these conditions, a low to high CLOCK transition will force the Q output high. The Q-NOT output will always be the opposite logic state of the Q output. State 2: The second low to high CLOCK transition forces the Q output low because the D input is low prior to the CLOCK transition. Remember that a high to low CLOCK transition has no effect upon any of the outputs. State 3: None of the outputs change state on the next low to high CLOCK transition because the D input is still low. State 4: The fourth low to high CLOCK transition forces the Q output back high because the D input is high at that time. State 5: The CLEAR input forces the Q output low regardless of the state of the CLOCK or D inputs. State 6: The PRESET input forces the Q output high regardless of the state of the CLOCK or D inputs. State 7: The final low to high CLOCK transition is ignored regardless of the D input state because it is overridden by the low PRESET input. |
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| 4.2 Separating the Channels: If you recall the command signal description in section 3.2, you will remember that each command signal is high for 1 to 2 milliseconds and low for 18 to 19 milliseconds. Also, if you recall the pulse stream description in section 3.3, you will remember that each command signal duration is bound by two low to high transitions within the pulse stream. Now we can put it all together and separate the command signals from the pulse stream using the one-shot, and the flip-flop digital logic circuits. |
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| The flip-flop circuit plays a vital role in separating the individual command signals and distributing them to their respective servos. In the receiver, there is one flip-flop circuit used for each channel in a cascading manner such that the Q output of the first flip-flop is connected to the D input of the second. Likewise, the Q output of the second flip-flop is connected to the D input of the third and so on. The clock input of all of the flip-flops are connected together, and also connected to the digital pulse stream that has been reconstructed by the receiver. That leaves a single input that is not connected to a driving source, which is the D input of the first flip-flop.
The first flip-flop of this cascaded chain is the one that "kicks off" the command pulse separation. Its D input is the only one that is connected to the Q! output of the one-shot circuit. For clarity, lets assume some initial conditions. We will assume that the Q outputs of all of the flip-flops as well as the one-shot are at a logic low state, and the beginning of the first pulse stream has not yet begun. If the Q output of the one-shot is low, then what is the state of the D input of the first flip-flop? Remember that its D input is connected to the Q! output of the one-shot, and the one-shot Q output is low. That makes the first D input high, right? Now, lets begin the pulse stream. |
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We start off with all Q outputs low, then along comes a low to high transition on the CLOCK signal. Only 2 outputs will change state regardless of how many flip-flops are in the chain. The Q output of the one-shot will transition low, and the Q output of the first flip-flop will transition high. The pulse stream signal will transition from high to low a short time later, but high to low transitions do not affect anything. With the Q output of the one-shot in a high state, the D input of the first flip-flop is now low. With the Q output of the first flip-flop high, so is the D input of the second flip-flop. Now, along comes the next low to high transition of the pulse stream. The one-shot is retriggered for another 3 milliseconds and does not change state. The Q output of the first flip-flop transitions low while the Q output of the second flip-flop transitions high. No other outputs change state. See how this works? The command signals are generated at the Q output of each flip-flop, and "ripple" through the flip-flop chain as the pulse stream transitions from low to high.
The command signal generation will continue until either the last flip-flop in the chain has completed generating its command signal, or the last pulse in the pulse stream frame has been generated. After the last pulse in the pulse stream has been sent, the pulse stream stays low for at least 6 milliseconds (worst case, assuming a 7-channel system). During that time, the one-shot will time-out and transition to its original stable state. The entire process starts over again with the beginning pulse of the next pulse stream. | ||
| 4.3 A Practical Example: There are many ways to design different circuits, and sometimes manufacturers use simple techniques to accomplish specific goals. Simple is good (as long as it is reliable) because the manufacturing cost savings makes products smaller and more affordable. The following example measurements were taken from an actual AM RC receiver. The flip-flop chain described above is commercially available in a single integrated circuit ("IC"). The CD4015 device is a shift register that is commonly used in pulse separation circuits. Specifications for this device can be downloaded from many different sources on the Internet, such as the device manufacturer at http://www.fairchildsemi.com. The device cost is about $0.35 in small quantities making it a good choice for a cost effective solution. |
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| Pin 1 of the 4015 device is the common CLOCK signal that is internally connected to all four flip-flop registers. This is where the baseband signal is connected. Pin 15 is the D input to the first flip-flop. In this case, the one-shot circuit is comprised of a simple resistor/capacitor/transistor combination as shown below:
In this example, transistor Q1 switches the voltage to 0 volts on the left side of resistor R1 when the baseband signal is high. Resistor R1 is a very low value and is only used to limit the current to a safe level when transistor Q1 turn on. When this happens, the voltage across capacitor C1 is driven to near zero volts. Resistor R2 is a relatively large value so that the voltage across capacitor C1 gradually increases when Q1 is turned off. The photo below shows the voltage waveforms at pin 15 of the 4015 device (top trace - R/C/T one-shot) and pin 1 (bottom trace - baseband signal). Each and every time the baseband signal is high, the D input to the first flip-flop is driven low. The amount of voltage charged across capacitor C1 is insufficient to be recognized a a high logic level as long as the frame pulses keep coming along and driving the voltage to near zero. Even when the pulse widths are expanded to 2.0 milliseconds, the voltage across C1 is still interpreted as a logical low level as shown in the photo below. The voltage across C1 does not charge to a substantially high level until the frame pulses stop coming. |
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Using this technique, the D input to the first flip-flop is always high prior to the arrival of the T0 pulse, and always low prior to the arrival of the T1, T2, T3, and T4 pulses. This chain can be expanded to several more channels by connecting the channel 4 output to an additional 4015 flip-flop device and properly connecting the baseband signal and other required logic levels (see 4015 device specifications for details). The following pictures show the flip-flop outputs for various channels and various pulse widths. | ||
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Baseband Signal |
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Servo Pulse |
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